Optimisation of Short Channel Strained Silicon Surrounding Gate MOSFET using Variable Oxide Thickness (VARIOT) for Low Power Application

This paper demonstrates an optimisation approach for strained Silicon Surrounding Gate MOSFET. The main contribution of this work is to determine the effective oxide thickness of the device using gate stacked insulator. Gate stack configuration plays a significant role in alleviating the leakage current and minimises the short channel effects. The thickness of the insulator layer is determined using the variable oxide thickness(VARIOT) technique. Using this method, the thickness of each layer which consists of SiO ₂ and high-k material will vary accordingly. In order to enable the transport properties of a short channel device, two models are invoked in TCAD simulators, namely Bohr Quantum Potential and velocity saturation model. Three types of high-k dielectrics were used such as Si ₃ N ₄ , HfO ₂ and AL ₂ O ₃ to determine the most advantages configuration on its device performance. It found that the gate stack with SiO ₂ /Si ₃ N ₄ configuration contributed the most improvement when it's lowering the leakage current and threshold voltage appreciably. The on-state current, threshold voltage and off-state current estimated about 1.2e-4, 0.17 V and 1e-8 accordingly. Moreover, the value of subthreshold swing (SS) and Drain Induced Barrier Lowering of the device approximately as 50 and 15, respectively, which is beyond the ideal case of conventional MOSFET.