XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Shihui Yin,Zhewei Jiang,Jae-Sun Seo,Mingoo Seok

IEEE journal of solid-state circuits（2020）

Cited 371|Views86

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Abstract

We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.

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Key words

Random access memory,Hardware,System-on-chip,Transistors,Computer architecture,Neural networks,Complexity theory,Binary weights,deep neural networks (DNNs),ensemble learning,in-memory computing (IMC),SRAM,ternary activations

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