A pattern-dependent injection-locked CDR for clock-embedded signaling

This paper presents a CDR architecture for clock-embedded signaling. To suppress the effect of data-dependent jitter of the conventional DLL-based approach, we propose a pattern-dependent injection-locking scheme in a PLL-based clock recovery circuit. It achieves both benefits of PLL and DLL, the input jitter filtering and the clearance of accumulated VCO jitter, respectively. A jitter analysis is also presented to develop a design strategy for the optimal extraction of injection timing from random data stream. The CDR, implemented in a 28 ​nm CMOS, achieves a data rate of 12.5 ​Gb/s with a 13.7 ​dB-loss channel and verifies the validity of the analysis.