A pure hardware-driven scheduler for enhancing bank-level parallelism in a persistent memory controller

Researchers are attempting to exploit the non-volatile nature of Persistent Memory (PM) in various applications. To utilize persistence, many solutions enforce strict, sequential write orderings that are propagated through the cache hierarchy, inevitably resulting in extra write requests. Other solutions introduce persistence logging operations to ensure transactional consistency, which also introduces extra writes. To rationally schedule these write requests, current work classifies the sources of write requests into subtypes at the software level based on the characteristics of the application, subsequently transferring the classified requests as hint messages to the memory controller level for guiding scheduling. However, categorizing diverse applications requires incompatible modifications to software and can degrade both the performance and fairness of the results with respect to low bank-level parallelism and low row-buffer locality. To address these problems, we bypass software intervention and propose PHD-scheduler, a Pure Hardware-Driven scheduler for enhancing bank-level parallelism in PM controller. PHD-scheduler is composed of three main ideas: (1) PHD-scheduler moves the classification into the PM’s controller level rather than intervening in the compatibility of the software, (2) it introduces a dynamic computing mechanism to ensure bank access from centralization to distribution, and (3) it maximizes row buffer locality by reshuffling memory requests with three novel criteria to achieve an appropriate batch scheduling. The experimental results show that PHD-scheduler achieves an average bank-level parallelism improvement of 11.8%. Moreover, performance and fairness are improved by 4.2% and 3.3%, respectively.