A One-to-Many Traffic Oriented Mm-wave Wireless Network-in-Package Interconnection Architecture for Multichip Computing Systems

High Performance Computing (HPC) platforms like blade servers consist of multiple processor chips, which may be multicore CPUs, GPUs, memory modules and other subsystems. In such memory and computation intensive systems one-to-many traffic patterns originate from cache coherency, system-level synchronization mechanisms and other control signals. However, small portions of such traffic can introduce huge local and global congestion, which significantly reduce overall performance and cause energy bottleneck unless low latency transmission is ensured by a one-to-many traffic-aware interconnection architecture. Therefore, these high performance and memory intensive multichip systems require efficient support for one-to-may traffic. Traditional metal-based Network-on-Chip (NoC) interconnection architecture is mostly designed for unicast traffic and therefore not suitable for such one-to-many traffic as it provides high-latency, power-hungry multi-hop paths. To address this issue, we propose the design of a one-to-many traffic-aware Wireless Network-in-Package (WiNiP) architecture by integrating a novel asymmetric wireless interconnection topology, a novel hybrid two-state Medium Access Control (MAC) and flow control. The proposed asymmetric topology, MAC and flow control collaborate with each other to form a low latency, one-to-many traffic-aware WiNiP interconnection architecture and increase system bandwidth with lower energy consumption. Through cycle-accurate simulator we show that the proposed topology reduces average packet latency by 47.92 % and outperforms other interconnection architectures for on and off-chip data transfer for synthetic as well as application-specific traffic patterns.