Efficient hybrid CMOS/memristor implementation of bidirectional associative memory using passive weight array

The primacy of memristors for the realization of the synaptic circuit makes this element a promising component for implementing Artificial Neural Networks (ANN). However, integrating memristors with other ANN components is still an open area of research. Therefore, a circuit-level hybrid CMOS/Memristor architecture for implementing Bidirectional Associative Memory (BAM) is proposed in this paper. A passive bi-directional pre-differentiation crossbar architecture has been utilized and applied for the realization of synaptic weights. A compact, low voltage CMOS neuron that consumes a low amount of power is also designed. The noise tolerance of the proposed hardware is evaluated for typical networks with different sizes and a number of stored patterns. It is demonstrated that the hardware pattern retrieval rate is similar to its software-based counterpart. The influence of memristor non-idealities on BAM is also investigated for the first time, and a practical method has been introduced to deal with this issue. In comparison to the available circuit-level hardware implementation of memristive associative memories, the proposed circuit consumes significantly less power and retrieves the stored patterns notably faster.