Efficient BIKE Hardware Design with Constant-Time Decoder

BIKE (Bit-flipping Key Encapsulation) is a promising candidate under consideration in the NIST Post-Quantum Cryptography Standardization process. It is a code-based cryptosystem with a simple definition and well-understood underlying security. The most critical step in this cryptosystem consists of correcting errors with a QC-MDPC linear code. Published performance on 64-bit processors shows this decode procedure takes 20M cycles for the software implementation, and worse for embedded devices. In this paper, we propose a BIKE coprocessor that accelerates the operations least suitable to embedded software implementation, enabling power-constrained SoC devices to directly implement BIKE with good performance. We propose a simplification of the grey-black decoder in the BIKE spec, which is more friendly to hardware implementations, and demonstrate the performance of this decoder on an Intel Arria 10 FPGA platform. Our implementation has a cycle-area performance comparable to other MDPC decoders in the literature, while including design elements which may facilitate power side channel resilience. The main result is to enable BIKE to be run on small SoC platforms, and therefore for those devices to resist attacks by quantum computers.