Optimization of GAA Vertical Nanowire Performance for Logic Application

In this work, we analyze the vertical GaN nanowire and investigate its logic performance and improvement through 3D simulation. The trapping effects are well analyzed and the curves are closely fitted to the experimental work. Further, this work suggested some methods to improve the logic performances by including the effect of m-plane side walls and optimizing the effects of dimension reduction. The performances improvement can be seen by the significant reduction in DIBL upto 40mV/V and SS upto 65 mV/dec.