Benchmarking Of Finfet, Nanosheet, And Nanowire Fet Architectures For Future Technology Nodes

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L-G) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrodinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L-G of 16 nm offering a larger on-current (I-ON) and slightly better sub-threshold characteristics. Below L-G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I-OFF), and the largest I-ON/I-OFF ratio out of the three architectures. However, the NW FET suffers from early I-ON saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.