Application of Piezoresistive Stress Sensor in Mold-1st Fan-out Wafer Level Packaging Processes

In semiconductor industry, it is very attractive to develop cracking free RDL, low warpage and high solder joint reliability FOWLP. Solder joint reliability is a big issue and can lead to interconnect failure, which is related to package design, material and assembly process. In this work, samples for reliability test have been prepared. Samples meet the criteria of each step, i.e. precompensation for less die shift, less wafer TTV, no chipping in dicing, ball shear measurement>122g, package level warpage <+/- 100um. For 6 types of samples, each type 22 samples are loaded into the TC chamber. 2 out of 132 samples are found to have open circuit issue after 250 cycles. 130 out of 132 samples all passed 500 cycles TC reliability test. In RDL process, dielectric or even metal line cracking are very common due to high localized stress concentration. How to measure the stress for the critical location and critical process steps is the crux of the matter. If critical location and the process step can be pinpointed, the package design parameters, materials and process parameters can be optimized in terms of stress value. In the present paper, metal 1 and via 2 layers have been tested for 3MTVs. Simulation validation has also been done for MTV2.