Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation

High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6% up to 30% more voltage drop tolerance.