Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs

IEEE Transactions on Electron Devices(2020)

引用 33|浏览6
暂无评分
摘要
In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-...
更多
查看译文
关键词
Logic gates,Etching,Solid modeling,Silicon,Analytical models,Silicon germanium,Fabrication
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要