Generation of the Verification Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism

In recent years, a high-level synthesis tool has been attracted in designing hardware circuits instead of conventional HDL. However, there exist two issues to implement a complex algorithm into hardware, which brings growing scale of a synthesized circuit and time for simulation. Therefore, though partitioning a circuit into multiple FPGAs is currently put into practical use, there are two constrains in implementation; the scale and the number of I/O blocks in an FPGA. Thus it is difficult to build a verification environment. In this study, we partition a circuit synthesized by a high-level synthesis tool into some reduced circuits. Moreover, the small circuits are equipped with self-verification function with generating a wrapper for each circuit verification. An FFT circuit which is generated by a high-level synthesis tool is partitioned by our proposed circuit partitioning mechanism. We verify the partitioned circuits in RTL simulation as well as implementation on an FPGA in order to confirm our targeted circuits are correctly operated.