Programmable Turbo Decoder Supporting Multiple Third-Generation Wireless Standards

A programmable turbo decoder is designed for multiple third-generation (3G) wireless communication standards. It mainly consists of a configurable SISO decoder and a 16-bit SIMD processor equipped with five processing elements and specialized instructions customized for interleaving. A fast and flexible incremental block interleaving algorithm that causes no timing overhead in changing interleaver structure is also proposed. The decoder occupies 8.90mm in 0.25μm CMOS with five metal layers, and exhibits the maximum decoding rate of 5.83Mbps.