Design and Implementation of Full Adder Cell with the GDI Technique Based on 0.18 mu m CMOS Technology

In this paper, The low power and high performance 1-bit full adder cell is proposed. The Gate Diffusion Input (GDI) technique has been used for the simultaneous generation of XOR and XNOR functions. Fourteen states of the arts 1-bit full adders and one proposed full adder are simulated with HSPICE using 0.18 mu m CMOS Technology at 1.8v supply voltage. The resulting full adder circuit is realized using of the 24 transistors, while having full voltage-swing in all circuit nodes. By optimizing the transistor size in each stage the power and delay are minimized. The results of post-layout simulation compared to similar reported ones illustrate significant improvement. Simulation results show great improvement in terms of Power-Delay-Product (PDP). The power consumption of this adder is 0.78 mu w.