Feature Selection for Instruction Placement in an EDGE Architecture

Communication overheads are one of the most important barriers to efficient parallel execution. In an Explicit Dataflow Graph Execution (EDGE) architecture, communication overheads are particularly important, as communication occurs at an instruction-level granularity. These communication overheads are exposed through the ISA, however, so the compiler can attempt to place instructions in a way that minimizes communication overheads while exploiting concurrency. The TRIPS prototype microarchitecture, an instantiation of an EDGE ISA, provides 16 functional units. The compiler maps hyperblocks of up to 128 instructions onto this execution substrate. Instruction placement involves selecting the best placement from among 128! possibilities, where b is the number of hyperblocks in the program. Because this search space is so large, we propose using reinforcement learning to find a placement function. To effectively use reinforcement learning, however, we must find the features that have the greatest impact on performance. For this project, we will focus on this feature selection aspect of the scheduling problem.