Analysis of Low Leakage and High Performance 4 bit CLA Full Adder

This paper presents implementation and analysis of ISCAS 85 74283 and various techniques minimizing the leakage current of ISCAS 85 74283, as leakage current has become a significant contributor of overall power dissipation of CMOS circuits. Various parameters such as effect of variation of supply voltage, width and threshold voltage and their impact on static power have been studied. Minimizing static power is major issue as static power has become comparable to dynamic power at sub-micron technologies. Various CLA is implemented on SPICE at 32nm technology. Leakage current reduction circuit techniques reduces considerable amount of power but may have various trade-offs in terms of delay and area