CBFD: A Count-Based Fault Detection Scheme for Memory Arrays

The performance-cost benefits enjoyed for decades due to the scaling of device area are challenged by power and reliability constraints. Fixed power envelopes and increases in static and dynamic variations have lead to higher probability of parametric and wear-out failures. This is particularly true for processor memory arrays, such as caches, that dominate the area of modern processors and are built with minimum sized SRAM cells that are prone to failure. It is, therefore, becoming essential to develop scalable cost-effective fault-tolerant techniques for processor memory arrays. Our attempt, presented in this paper, to address scalable memory array fault tolerance is a novel error detection scheme that relies on a count-based method, called CBFD (count-basedfault-detection), that provides the number of 1s(0s) in an array at any given time. The state overhead of the method is (log2k) + 1 bits for an array with k bits. For fault-free array operation a basic invariance is maintained by the method: the number of 1s(0s) never exceeds the array size or becomes negative. This invariance can be violated when there is a fault. The paper introduces the count-based method and explain its detection latency, overheads, and fault coverage. It also discusses how it can be used to detect soft and hard errors both in array cells and peripheral logic.