Automated di / dt Stressmark Generation for Microprocessor Power Distribution Networks

In this paper, we propose a method for automated di/dt stressmark generation to test maximum voltage droop in a microprocessor power distribution network. The di/dt stressmark is an instruction sequence which draws periodic high and low current pulses that maximize voltage fluctuations including voltage droops. In order to automate di/dt stressmark generation, we devise a code generator with the ability to control instruction sequencing, register assignments, and dependencies. Our framework uses a Genetic Algorithm in scheduling and optimizing candidate instruction sequences to create a maximum voltage droop. The simulation results show that our automatically generated di/dt stressmarks achieved more than 40% average increase in voltage droop compared to hand-coded di/dt stressmarks and typical benchmarks in experiments covering three micro-processor architectures and five power distribution network (PDN) models. Additionally, our method considers all the units in a microprocessor, as opposed to a previous ILP scheduling method that handles only execution units.