Upgrade development progress for the cern sps high bandwidth transverse feedback demonstration processor

A high bandwidth feedback demonstrator system has been developed for proof of concept transverse intra-bunch closed loop feedback studies at the CERN SPS. The system contains a beam pickup, analog front end receiver, signal processor, back end driver, power amplifiers and kicker structure. The main signal processing function is performed digitally, using very fast (4 GS/s) data converters to bring the system signals into and out of the digital domain. The digital signal processing is itself implemented in an FPGA allowing for maximum speed and flexibility. The signal processor is a modular design consisting of commercial and custom components. This approach allowed for a rapidly-developed prototype to be delivered in a short time with limited resources. Initial beam studies at the SPS using the system prior to the CERN long shutdown one (LS1) have been very encouraging. Building on this success, we are planning several key upgrades to the system, including the signal processor. This paper describes these key upgrades and reports on their progress. OVERVIEW AND UPGRADES TO THE DEMONSTRATION SYSTEM The high-current operation of the SPS for HL-LHC injection will require mitigation of possible Ecloud and TMCI driven intability effects [1]. A single-bunch wideband digital feedback system ( Fig. 1) was initially commissioned in November 2012 and used through the February 2013 SPS LS1 shutdown. During the CERN LS1 interval we are upgrading the Demonstration system to add functions necessary to validate a full-featured control system.