Advanced Circuit Interface for Maintaining Performance in Systems with Multiple Voltage Domains

Multi-level voltage scaling is one of the most effective techniques for reducing power without sacrificing speed in an integrated circuit (IC). However, additional circuitry is required at the interfaces of the circuit blocks which operate at different voltage levels. These circuits impose a significant delay overhead and restrict the use of multi-voltage scaling at blocks where critical paths traverse their interfaces. A by-pass circuit is proposed to alleviate these timing issues under specific operation conditions. The new circuit results in significant performance improvements of up to 89% and power reduction up to 52% compared to a traditional feedback-based level-up shifter in a 32 nm technology node. Furthermore, greater performance and power savings are demonstrated when more cells are being bypassed, such as the isolation cells.