Inferring Timed Message Sequence Charts from Execution Traces of Large-scale Component-based Software Systems

This paper introduces a new measurement-based approach to get insights in timing bottlenecks of existing largescale component-based software systems. As a foundation we formalize a subset of the Message Sequence Charts standards (Z120 and UML2.0) called Timed Message Sequence Charts (TMSC). TMSCs capture the execution of component-based software systems in an intuitive way and are amenable to formal timing analysis. We introduce a scalable heuristicsbased technique to automatically infer TMSCs from execution traces. We demonstrate the effectiveness of our approach by automatically computing critical paths in the software of an industrial lithography scanner to identify timing bottlenecks.