Comparative analysis of multiplier and multiplier-less method used to implement fir filter on fpga

Finite impulse response (FIR) filters are a type of digital filter that has a finite impulse response which is used in a communication system and signal processing. FIR filter structure consists of a multiplier, adder, and delay element. The multiplier is one of the key blocks in most digital systems which consume high power and more area. In this paper, FIR filter is implemented using both Multiplier and Multiplierless method. In multiplier method, Modified Booth and a Modified Booth with Wallace tree multiplier is designed while in the multiplier less method, distributed arithmetic and distributed arithmetic with partition is designed using Verilog. The code is simulated in Model Sim and synthesized in Xilinx 14.7. This paper summarizes the comparative study of the multiplier and multiplier-less method based on various parameters. There is a trade-off between area and delay. This paper will help to choose the best method according to the requirement.