Delay Analysis of an Atm Switch for Continuous-bit-rate Traffic

In this paper, we model a packet multiplexer for Continuous Bit Rate (CBR) traffic in an A TM network as a nD / D /1 queue. We compare the efficiency of various algorithms for finding the delay distribution. In particular, we propose a new algorithm whose time complexity is O(n2) where n is the number of voice sources being multiplexed. Further, the use of the central limit theorem can reduce the time complexity to 0 (n) for large n. We find an asymptotic formula whose time complexity is independent of n and it wodes well (for practical purposes) over a wide range of parameter values. We examine and comment on the use of the MI Dll results as an approximation. In addition to comparing the performance of these algorithms, we show that the buffer requirements for such a queue is significantly less than the theoretical maximum (even when the requirement on the call disruption probability is very low). This result has important implications in the design of buffer size. Further, the buffer requirement is relatively insensitive to the design criterion (call disruption probability) so that inaccuracies in measurements and/or traffic forecasts will not lead to erroneous design.