A 16-Bit Hybrid Adc With Circular-Adder-Based Counting For 15 Mu M Pitch 640x512 Lwir Fpas

A hybrid Analog to digital converter (ADC) is presented for long-wave infrared focal plane arrays. A two-stage quantization structure is applied in the folding integration process, which results in better chargehandling capacity and higher linearity compared with conventional designs while using fewer transistors at the pixel level. By employing a circular-adder-based counting structure with 3T dynamic memory cells, hardware consumption can be reduced. A pixel circuit of pitch 15 mu m has been designed using the 0.18mm Complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the pixel-level ADC is 0.214 mu W, and the charge-handling capacity is 1Ge(-). Simulation results demonstrate a signal-to-noise ratio of 90dB and a nonlinearity of 0.11%.