Output-Capacitorless Tri-Loop Digital Low Dropout Regulator Achieving 99.91% Current Efficiency and 2.87 fs FOM

This article presents an output-capacitorless digital low-dropout regulator (OCL-DLDO) for fine-grained on-chip power delivery and management in system-on-chip devices. The proposed OCL-DLDO incorporates three distinct feedback loops: asynchronous, coarse, and fine loops. The asynchronous loop is activated during drastic load transients, rapidly restoring the output voltage and achieving a small voltage undershoot even without any output capacitor. The coarse loop, which is equipped with adaptive gain adjustment logics based on least-mean-square algorithm, adaptively adjusts the connection of power switches for fast and accurate voltage regulation. Lastly, the fine loop, which is implemented with shift-registers-based control, takes over the control in steady-states for low output voltage ripples and quiescent current. The proposed OCL-DLDO was fabricated in 65 nm CMOS process with an active area of 0.041 mm ² . The measurement results show that the proposed OCL-DLDO achieves a peak current efficiency of 99.91% and a figure-of-merit as low as 2.87 fs when driving 25 mA of load current.