Lower Bounds on Power Consumption of Clock Generators for ADCs

This paper formulates the jitter-power trade-offs in the design of phase-locked loops that provide the sampling clock for ADCs. We obtain lower bounds for the oscillator power consumption in terms of the performance penalty allowed for the ADC. We show that the oscillator power grows with the square of the target signal-to-noise ratio and the square of the clock frequency and is expected to exceed that of the ADC in future designs.