Improving the electrical performance of Cu/CVD low k Coral(TM) interconnection - An exploration of SiC cap etch and Ta diffusion barrier deposition

Integration of Cu with low k dielectrics has been practicing for back-end-of-line (BEOL) process in order to reduce both RC delay and decrease parasitic capacitance of interconnections. In this paper, impact of key processes of 130nm Cu/Coral(TM) integration, viz., cap etch and diffusion barrier deposition on electrical and reliability performance was reported. Not only did optimized SiC cap etch result in better control of via resistance distribution, but it improved reliability performance without formation of "overhangs" . We also demonstrated use of high flow low bias (HFLB) Ta deposition improved electrical performance and dielectric breakdown strength of BEOL interconnects.