Line Edge Roughness due to Oxide Rie Process
2019 30TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC)(2019)
摘要
The performance of a subset of the logic devices on a recent new design showed unexpected variation. Analysis showed that the nitride/oxide spacer exhibited excessive roughness in certain areas of a logic chip, causing the observed device shift. To execute the experiments required to correct the issue we developed a method to use inline measurement to quantify spacer quality. This helped to improve spacer quality without delaying availability of the product.
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