K. Koukos A. Ros E. Hagersten

Memory access latency has become one of the major bottlenecks to system performance. To hide memory access latency, researchers have proposed hardware data prefetching mechanisms. Prefetching refers to fetching data from memory into caches or a prefetching buffer before actually using them. In this way, the memory latency can be effectively hidden and the processors performance can be improved. Data prefetching techniques in conventional single-core processors have been proven useful. However, on a chip multiprocessor (CMP) system, all running threads usually share the last level cache (LLC) and off-chip memory. Memory requests from each core conflict with those from other cores, since prefetching requests need to traverse on-chip interconnect networks and the memory bus to arrive at memory banks as normal data requests. The presence of a prefetching engine would cause additional cache …