Optimization of Double Gate Vertical Channel Tunneling Field Effect Transistor (DVTFET) with Dielectric Sidewall

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage (V-amb) and double gate structure is applied to improve on-current (I-ON) and subthreshold swing (SS). We discussed the fin width (W-S), body doping concentration, sidewall width (W-side), drain and gate underlap distance (X-d), source doping distance (X-S) and pocket doping length (X-P) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high I-ON of 1.2 x 10(-3) A/ mu m and low V-amb of -2.0 V.