An Approach to Predict 4H-SiC Wafer Bending after Back Side Thinning by Substrate Resistivity Analysis

It is commonly thought that, in the development of SiC power devices with low on-state resistance (R on ), several critical processes in the device fabrication line can strongly impact the final warpage of wafers. High warpage would lead to bad definition of masks, preventing uniform deposition of resist materials and disturbing the normal handling procedures. All these factors would then result in a potential decrease of the electrical yield of the devices, especially for MOSFETs. This study reveals the lack of correlation between critical line processes such as epitaxial growth, oxidations, ion implantations, annealing processes with the final bending of wafers. Conversely, a strong dependence with the resistivity of the substrates is observed. A new parameter defined as RMR (Resistivity Modulation Rate) is taken proposed and, together with the starting value of ingot resistivity, this parameter shows a strong relationship with the final warpage after wafer thinning. A safe region having warpage low enough to allow the workability of the wafers is found.