A Power-Efficient 10-MHz Bandwidth Active-RC CTDSM with a Charge-Recycled Highly-Linear 5-Level SC DAC

Active-RC continuous-time Delta-Sigma modulators (CTDSMs) are an attractive solution for power-efficient and precise analog-to-digital conversion. Multi-bit CTDSMs offer reduced jitter sensitivity and lower oversampling ratios, which make them suitable for wideband applications compared to their single-bit counterparts. However, they suffer from the problem of element mismatches in their digital-to-analog converters (DACs). On the other hand, in state- of-the-art CTDSMs, the DACs can consume a significant percentage of the overall power. In this manuscript, we present an active-RC CTDSM with a novel 5-level highly linear switched-capacitor (SC) DAC, which reduces power consumption through charge recycling. Splitting a DAC capacitor into two halves helps avoid harmonic distortions caused by signal-dependent timing of DAC pulses. A 10-MHz bandwidth modulator with an 800-MHz sampling frequency (f(S)) is designed in a 65-nm CMOS technology. Transistor-level simulations show that it achieves 75.9 dB SNDR and 88.8 dB SFDR while consuming 1.28 mW from a 1.2-V supply. Despite the DAC being of the SC type, the modulator achieves high aliasing rejection ratios of 68.8 dB and 65.9 dB at f(S) and 2f(S), respectively.