Drain-engineered Vertically Stacked Junctionless FET Exhibiting Complementary Operation

In this work, a multifunctional drain-engineered (DE) vertically stacked (VS) junctionless (JL) FET exhibiting device reconfigurability and its application as an inverter are proposed and simulated. The proposed DE VS JL FET consists of stacked $${n}^{+}$$ and $${p}^{+}$$ device layers having SiO $$_{2}$$ isolation vertically, with n-drain ( $${D}_n$$ ) and p-drain ( $${D}_p$$ ) silicide regions connected together. Highly doped device layers allow for the formation of a thin-dopant segregation layer on the drain side. To mimic the realistic channel/drain junctions, silicides with realistic Schottky-barrier heights are chosen ( $${D}_n$$ : $$\hbox {ErSi}_x$$ $$\approx $$ 0.28 eV and $${D}_p$$ : PtSi $$\approx $$ 0.24 eV). Both device layers contribute individually to the n-FET and p-FET complementary operation when biased adequately. Moreover, the transient analysis shows that the device in the inverter mode performs reasonably well even when the $${V}_{\text {DD}}$$ is scaled up to 0.5 V. Furthermore, a 3-transistor-based 2-input XOR gate standard cell has also been realized using the proposed device.