A 1200v/650v/160a Sic+Si Igbt 3-Level T-Type Npc Power Module With Optimized Loop Inductance

Three-level inverters suffer from higher parasitic inductance due to the increased number of series-connected power switches in a single current commutation loop (CCL) and geometrically larger size of CCL with compared to their 2 level counterparts. As such semiconductors are subjected to higher voltage stress and severe ringing at the switching transient. To solve this problem, an optimized 3-level T-type NPC power module has been proposed with a hybrid combination of the switch (SiC MOSFET + Si IGBT) rated for 1200V/180A. A step by step design methodology has been presented in this work. A stacked DBC with via has been utilized to have a vertical power loop as such, lower loop inductance. All the commutation loop has been identified and corresponding loop inductances have been optimized as low as 4.5 nH and dynamic current sharing between paralleled devices has been ensured.