A Reliable TDDB Lifetime Projection Model Verified Using 40Mb STT-MRAM Macro at Sub-ppm Failure Rate To Realize Unlimited Endurance for Cache Applications

V. B. Naik,K. Yamane,J. H. Lim,T. Y. Lee,J. Kwon, Behin Aein, N. L. Chung, L. Y. Hau,R. Chao,D. Zeng,Y. Otani,C Chiang,Y. Huang,L. Pu,N. Thiyagarajah,S. H. Jang, W. P. Neo,H. Dixit, L. C. Goh,T. Ling,J. Hwang, J. W. Ting,L. Zhang,R. Low, N. Balasankaran,C. S. Seet,S. Ong,J. Wong, Y. S. You, S. T. Woo,S. Y. Siah

symposium on vlsi technology（2020）

引用 3|浏览9

暂无评分

摘要

We report a reliable TDDB lifetime projection model using power law verified from 40Mb STT-MRAM macro at sub-ppm failure rate to realize nearly unlimited endurance for cache applications. A specially designed macro, having internal temperature control systems and capable of applying accelerated voltage at 40Mb array level with wide operating temperature range: -40~125 °C and varying pulse widths: 200~10 ns, is used for the study. We demonstrate a superior endurance performance of > 1 E 12 cycles at 1 ppm failure rate using 40Mb macro combined with SRAM -like MTJ stack with lower operating voltage at BER ~ 1 ppm at 1 0 ns write pulse.

查看译文

关键词

temperature control systems,wide operating temperature range,superior endurance performance,STT-MRAM macro,sub-ppm failure rate,TDDB lifetime projection model,SRAM -like MTJ,temperature -40.0 degC to 125.0 degC

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要