A 14.7Mb/mm² 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference

El Mehdi Boujamaa, Samsudeen Mohamed Ali,Steve Ngueya Wandji,Alexandra Gourio,Suk-Soo Pyo,Gwanhyeob Koh,Yoonjong Song,Taejoong Song,Jongwook Kye, Jean-Christophe Vial, Andrew Sowden,Manuj Rathor,Cyrille Dray

2020 IEEE Symposium on VLSI Circuits（2020）

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摘要

In this paper we present a read circuitry that tackles all STT-MRAM read challenges. First, a negative temperature coefficient (NTC) reference based on an MTJ in series with an “NTC” resistor circuit emulator is described. Then, an offset cancelled voltage sense amplifier using low read current and reference averaging is discussed. Measurement results show a maximum of 2% reference impedance error (vs. ideal) and 1.7% read error rate degradation (vs. technology intrinsic defectivity rate). A 14.7Mb/mm ² memory density is also achieved, which is the best STT-MRAM published density for embedded applications.

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关键词

NTC resistor circuit emulator,offset cancelled voltage sense,current reference averaging,read error rate degradation,memory density,STT-MRAM published density,current starved read path,fully trimmable CTAT reference,negative temperature coefficient reference,technology intrinsic defectivity rate,reference impedance error,size 28.0 nm

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A 14.7Mb/mm2 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference

A 14.7Mb/mm² 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference