A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor
2020 IEEE Symposium on VLSI Circuits（2020）
摘要
A proactive clock-gating system (PCGS) in a 7nm Qualcomm̅ Hexagon™ digital signal processor (DSP) predicts supply voltage (V
DD
) droops based on microarchitectural events and a power-delivery-network (PDN) model and adapts clock frequency (F
CLK
) to reduce the V
DD
droop. Silicon measurements demonstrate 10% higher F
CLK
or 5% lower V
DD
.
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关键词
proactive voltage-droop-mitigation system,proactive clock-gating system,supply voltage,microarchitectural events,PCGS,Qualcomm̅ Hexagon digital signal processor,clock frequency,power-delivery-network model,PDN model,voltage droop reduction,silicon measurements,size 7.0 nm
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