Identification of an Entire Workload's CPU-Vmin from the n-First Seconds of its Execution Based on Performance Counters
2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)(2020)
摘要
CPU pessimistic voltage margins set by hardware designers to address voltage-noise, aging and static variations, limit the power efficiency of computing systems. These margins are necessary to avoid voltage emergencies that lead to silent data corruption and application/system crashes which are not acceptable in most situations. However, the voltage margins required by different applications may vary and, therefore, an opportunity may exist to improve the power-efficiency if we can adapt the CPU voltage margins per workload. This paper presents a comprehensive correlation analysis of an application's minimum operating voltage (CPU-Vmin) with hardware's performance counters on a real multicore system. The analysis reveals that a subset of the performance counters-the same ones across different workloads-have a strong correlation with a workload's CPU-Vmin. Moreover, the results show that the CPU-Vmin is accurately identifiable by monitoring a workload's performance-counters during the n-first seconds of its execution. Our findings serve as the basis of a software-based CPU-Vmin identification method that monitors an application for the first n-seconds and then sets the CPU supply voltage to a specific value for the rest of the execution. Our evaluation shows that when n-first equals to 20 seconds, the CPU-Vmin workload identification method provides a safe CPU-Vmin, 99.4% of the time and reduces power on average by 3.8% and 7.1% as compared to when operating at a safe and a nominal supply voltage, respectively.
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关键词
CPU-Vmin, identification, CPU-Vmin characterization, correlation analysis, performance counters, voltage emergencies, operation at lower voltage margins, power savings, reliability improvement.
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