A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow

Asynchronous quasi-delay-insensitive circuits are known for their robustness against variations, but their widespread use has been prey to the absence of adequate design methods and lack of design and verification tools. The recently proposed Pulsar flow enables the design and optimisation of quasi-delay-insensitive circuits using conventional EDA tools, enhanced by adequate libraries, methods and models. Pulsar enables designers to naturally trade performance for power or area, whenever there is slack in timing budgets. However, Pulsar lacked an automated dual-rail expansion method to support its operation, requiring that designers manually develop a timing model as input to the computation of asynchronous cycle time constraints. This paper proposes and describes the features of a frontend for Pulsar. Pulsar-F, the new flow version can be used as a push-button design tool for asynchronous QDI circuits. Pulsar-F adds the following features to Pulsar: (i) an RTL-based design capture method; (ii) a heuristic, timing-driven singlerail pre-synthesis process using commercial EDA tools; (iii) a dual-rail expansion technique with fine-grain acknowledgement network generation; (iv) a tool that automates the computation of the Hal-Buffer Channel Network (HBCN) graph-based timing model for pre-synthesised circuits and derives a set of timing constraints for it. Experiments show that Pulsar-F improves Pulsar to further aid asynchronous designers to trade off power, area and performance.