Exceedingly High Performance Top-Gate P-Type Sno Thin Film Transistor With A Nanometer Scale Channel Layer

Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (mu(FE)) and large on-current/off-current (I-ON/I-OFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high mu(FE) of 4.4 cm(2)/Vs, large I-ON/I-OFF of 1.2 x 10(5), and sharp transistor's turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related mu(FE) were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn-O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole mu(FE), I-ON/I-OFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.