Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion

Youngchang Choi,Sunmean Kim,Seunghan Baek,Seokhyeong Kang

2020 International SoC Design Conference (ISOCC)（2020）

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摘要

A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.

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关键词

4-trit ternary DAC,power consumption,ternary data conversion,current-steering ternary DAC,conventional binary DAC,low-power 4-trit current-steering DAC,6-bit binary DAC,CMOS technology,size 180.0 nm,voltage 1.8 V

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