Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications

In this paper, gate-stacked gate-material-engineered junctionless nanotube MOSFET (GS GME JL NTMOSFET) was proposed for digital circuits. In GS configuration, hafnium-based high-k dielectrics (HfO 2 and Hf x Ti 1− x O 2 ) were used in gate-stacked engineering (for inner as well as outer gate oxide). The performance of proposed device was compared with non-stacked GME JL NTMOSFET and analysed. GS GME JL NTMOSFET offered a significant reduction in leakage current (~ 10 –16 ) and improvement in I ON / I OFF ratio (~ 10 11 ) as compared to non-stacked device. It was found that side spacer with suitable dielectric constant can be considered to improve the I ON / I OFF ratio, SS, DIBL of the proposed device. Furthermore, the CMOS inverter circuit of purposed device was designed to investigate its digital performance. Therefore, GS GME JL NTMOSFET with adequate design parameters and dielectric material may be used in future digital applications.