11.7 A 56Gb/s 50mW NRZ Receiver in 28nm CMOS

The power consumption of wireline transceivers has become increasingly critical as higher data rates and a larger numbers of lanes per chip are sought [1] -[6]. While attractive for lossy channels, PAM-4 signaling has mostly dictated ADC-based receivers (RXs) and relatively high power consumption [1], [2]. Non-return-to-zero (NRZ) receivers, on the other hand, can be realized in the analog domain, potentially consuming less power, but they must deal with a greater loss. This paper introduces an NRZ RX that achieves more than a twofold reduction in power while exhibiting BER <; 10 ^-12 for a channel loss of 25dB at 28GHz. The proposed design can compete with PAM-4 counterparts and/or serve in 112Gb/s systems that must also support 56Gb/s reception. Figure 11.7.1 shows the RX architecture. The data path consists of a CTLE core, a DFE core, a discrete-time linear equalizer (DTLE) [4], and a DMUX. The receiver performance is greatly improved by a number of feedforward and feedback paths. Also proposed is a half-rate “band-pass” CDR that avoids loading the main data path and the use of quadrature VCOs.