High performances 3D heterogeneous integrated devices based on 3D silicon capacitive interposer

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)(2020)

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摘要
One of the key issues in today's 3D integration topic is to correctly design and assemble silicon-related technologies (ICs, IPDs, Si-interposers and so on) with non-silicon-related technologies (ceramic components, plastic molded chips, crystal oscillators as examples), in a structure that takes advantage of the silicon base, like thin-pitch TSVs, RDL or WLCSP. Such structure would help moving from the COB era, to a real 3D heterogeneous platform era. Two successful examples, with high integration level and optimized performances, will be detailed in this paper.
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关键词
Integrated Passive Devices,Through-Silicon Via,Wafer Level Chip Scale Package,Heterogeneous assembly,Silicon Interposer with Embedded Trench Capacitors
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