Comparative Analysis of MOSFET and FinFET Based Full Protected Soft Error Tolerant Latch

Average power and delay are two essential aspects of measuring device performance in integrated circuits. The tradeoff between the two for a full protected soft error tolerant latch has been observed for MOSFET and two different operating modes of FinFET across 45nm and 32nm technology nodes and a comprehensive comparative analysis has been provided in this paper. The simulations have been conducted on HSPICE simulator and the results show as much as 84% reduction in delay with almost 8 times increase in power consumption for SG FinFET operation. A 13% improvement in power delay product was observed using LP FinFET mode in comparison with prevalent MOSFET technology. The design consideration of device choice and operation mode was also discussed.