Minimization of Switching Activity of Graphene Based Circuits

Reduction of power dissipation is a key challenge of VLSI circuits designers. In traditional CMOS-based circuits, dynamic power dissipation occurs due to the switching activity, i.e., transitions at logic nodes. In graphene-based circuits, power dissipation is also caused by the switching activity. In this paper, we compute the switching activity of these circuits considering the switching at every transistor. We propose an algorithm to minimize the total switching activity of graphene-based logic circuits. The algorithm is tested on benchmark circuits and the results show the reduction of average switching activity, area, and switching activity x area respectively by 9.17%, 0.81%, and 9.82%