Time Evolution of DIBL in Gate-All-Around Nanowire MOSFETs During Hot-Carrier Stress

Anshul Gupta,Charu Gupta,Anabela Veloso,Bertrand Parvais,Abhisek Dixit

IEEE Transactions on Electron Devices（2021）

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摘要

The influence of hot-carrier degradation (HCD) on lateral trap distribution within the device channel is experimentally investigated for gate-all-around nanowire (NW) nFETs. In particular, using drain-induced barrier lowering (DIBL) as the parameter, the damage caused by hot-carriers (HCs) is monitored for devices with different geometries, including fin width and gate length. It is observed that ...

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关键词

Degradation,Logic gates,Stress,Semiconductor device measurement,Hot carriers,Performance evaluation,Gallium arsenide

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