A dual-residue pipelined SAR ADC using only zero-crossing signals

This paper presents a dual-residue pipelined successive approximation register (SAR) A/D converter (ADC) that relaxes the accuracy requirement for residue amplifications and thus enables use of only zero-crossing (ZX) signals for the benefits of power efficiency and technology scalability. The dual-residue architecture is illustrated with design of an 11b two-step pipelined ADC consisting of 8b coarse and 5b fine (with 2b over-range) SAR sub-ADCs, which resolve 2b and 1b per SAR conversion cycle, respectively. Two ZX signals (or dual-residues) in opposite polarities automatically available in each 2b SAR cycle are sampled and held at the end of the coarse conversion for use as the full-scale reference for the fine SAR that quantizes a fixed input of zero. Simulations show that the ADC in 45 nm CMOS using typical open-loop circuits for inter-stage residue operation can achieve ENOB > 10 at 400 MS/s and Schreier FoM = 171.4 dB without residue gain calibration.