Reference Voltage Buffer For Hybrid Rc-Dac Sar Adcs In 130 Nm Cmos Process

Fast settling, accurate reference voltage buffer (RVB) are one of the key blocks of a successive approximation register (SAR) ADC. This paper presents the design of a RVB, which is aimed to drive SAR ADC architectures with hybrid RC-DAC: a popular implementation for area and power efficient solution. The design challenges associated with the RVB implementation are also discussed using a 12-bit, 8 MSPS SAR ADC as a test vehicle. Implemented in 130nm CMOS process, the buffer operates from a 1.2V supply and consumes 760 mu A current while occupying 1530 mu m(2) of area. It is capable of settling to better than 12-bit accuracy within 3.9 ns and has a total output noise of 87 mu V. Post-layout simulations together with the entire SAR ADC shows a ENOB of 11.5-bits thus confirming that the proposed reference voltage buffer serves the targeted application.